The ever-growing increase in global internet traffic imposes significant challenges on data center operators. An almost exponential growth is found for both intra- and inter-data center traffic originating from the continuous growth of cloud-based applications, social media and big data analytics. Modern data centers utilize hundreds of thousands of servers which require an efficient interconnection network which is both low-cost and energy-efficient.
Network topology requires that all server nodes are connected to each one via a set of switches arranged in several hierarchy layers. Since the network is designed as a non-blocking Clos network, the number of switch ports must be large enough to support the entire data center traffic without any congestion created.
As a result, the bandwidth of switches deployed doubles itself every 2-3 years with 12.8 Tera-bits per second (Tb/s) being the largest bandwidth in use today and 25.6 Tb/s scheduled to arrive by 2020.
The number of input/output (IO) ports on these large switch application specific integrated circuits (ASICs) is limited by package and printed circuit board (PCB) design rules, with 256 ports being the upper limit, so far. Thus, to comply with the need for more bandwidth, the line rate of these ports has been constantly rising: 3.2 Tb/s switch using 128 ports running at 25 Giga-bits per second (Gb/s); 6.4 T switch using 256 ports at 25 Gb/s and 12.8 T switch using 256 ports at 50 Gb/s.
With 25.6 T switches, there will be 256 ports running at 100 Gb/s (50 G Baud, four-level pulse amplitude modulation (PAM4)).
FIG. 1 illustrates a prior art line card 1.
Switch 2 is mounted on a line card 1 is connected via its IO ports to the front panel optical transceivers 4 using metal traces 5 in the PCB. Transceiver 4 converts the electronic signal to an optical signal coupled into fiber optic link 6.
The loss increases with the line rate and at 100 Gb/s amounts to about 25 dB per link. This loss needs to be overcome by a serializer-deserializer (SerDes) interface on the switch 2 to enable traffic flow.
However, the power consumption of such a SerDes interface is in the order of 1 W/100G using advanced CMOS nodes with a 20-30% drop expected with further scaling of the process node.
With a 256 SerDes interface array in the switch ASIC, the chip IO power amounts to 180-250 W. This is almost 50% of the total ASIC power implying that the switch capacity is seriously reduced compared to the amount of logic processing that could be carried out.
A second limitation is associated with the power dissipation of the 4×100 G front panel transceiver 4 that performs an e/o conversion of the highly attenuated and distorted 100 G signal.
A customized DSP is required to filter the incoming signal using a multi-tap DFE equalizer. This step comes at additional power dissipation of about 1 W per transceiver and with 32 devices on the front panel, the total power dissipation on traffic flow in system 1 exceeds 280 W